As electronic components and the internal structures in integrated circuits continue to become smaller, it has become easier to either completely destroy or otherwise impair electronic components. In particular, many integrated circuits are highly susceptible to damage from the unintended discharge of static electricity, generally as a result of handling or from physical contact with another charged body. Electrostatic discharge (ESD) is the transfer of an electric charge between bodies at different electrostatic potentials (voltages), caused by direct contact, or induced by an electrostatic field. The discharge of static electricity has become a critical problem for the electronics industry.
Device failures that result from ESD events are not always immediately catastrophic or apparent. Often, the device is only slightly weakened but is less able to withstand normal operating stresses and, hence, may result in a reliability problem. Therefore, various ESD protection circuits should be included in the device to protect the various components.
When an ESD discharge occurs onto a transistor or other semiconductor element, the high voltage and current of the ESD pulse relative to the voltage- and current-sustaining capabilities of structures within the device can break down the transistor and potentially cause permanent or latent damage. Consequently, circuits associated with input/output pads of an integrated circuit need to be protected from ESD pulses so that they are not damaged by such discharges.
Integrated circuits and the supporting device geometries which form the integrated circuits continue to be reduced in size. The physical dimensions of transistor structures limit the voltage that the transistor can withstand without damage. Thus, as semiconductor devices are formed with fine-line structures, breakdown voltages of transistors therein and other circuit elements are lowered, and currents capable of overheating components are more frequently reached by the voltages and currents induced by an ESD event. Additionally, recent advances in technology have produced devices which can fail at voltage levels lower than the triggering voltages of known ESD protection circuits. As an example, modern CMOS processes, particularly fine-line processes including lightly doped drain extension structures, are required to support low-voltage designs such as circuits that operate with bias voltages of 1.5 volt or lower, and also support higher voltage capabilities, such as analog and mixed signal outputs at voltages such as 12 volts. This allows design of highly integrated products with both digital and analog mixed-signal functionalities, for example, line drivers in a telecommunications device. Such designs present a narrow window of voltage in which ESD protection must be provided. A voltage clamping device is required for an ESD event wherein a clamping voltage is lower than a breakdown voltage of protected circuit parts, such as a drain-extended MOS (DEMOS) driver stage in a telecommunications device that may require protection with a clamping voltage between 15 and 22 volts, for example, for a 12-volt rated device.
In conventional technologies, fine-line products (e.g., products constructed with a 130 nm or finer technology) with high voltage CMOS protection requirements above 10 volts have either been implemented in older technologies with larger feature sizes (e.g., with a 250 nm or larger technology) with appropriately higher breakdown voltages, or have been realized with a system-in-package (SIP) approach wherein a low voltage part is implemented in an advanced technology (e.g., in a 130 nm technology), and the high voltage part in a 250 nm, or even a 0.35 μm, technology. Both solutions suffer from cost disadvantages.
Thus, there is a need for small, compact, ESD protection circuits capable of economically protecting low-voltage circuits that include high voltage capability.